1. Field of the Invention
The present invention relates in general to the field of information processing, and more specifically to a system and method for stabilizing an analog-to-digital converter delta sigma modulator using an internal stabilizer path having a direct output-to-integrator of loop filter connection.
2. Description of the Related Art
Many electronic systems employ signal processing technology to process analog, digital, or a mix of analog and digital signals. In audio applications, an analog-to-digital conversion process often involves oversampling a signal, modulating the signal using a delta-sigma modulator to shape noise associated with quantizing the signal, and filtering the delta sigma modulator output with a digital filter. The filtered output signal used in a variety of ways, such as stored as digital data, transmitted, or used to subsequently produce an analog signal suitable for driving a load such as a speaker.
Delta-sigma modulators receive an input signal and convert the signal into a series of low resolution pulses having an average amplitude over time proportional to the input signal. In the process of producing a modulated output signal, delta-sigma modulators introduce quantization noise into the modulated input signal. However, the quantization noise advantageously resides outside of the audio baseband where frequency components of interest reside, i.e. between about 0 Hz and above about 20-25 kHz. Thus, in an audio context, “in-band” refers to frequencies between 0 Hz and about 20-25 kHz, and out-of-band frequencies refer to frequencies above the maximum in-band frequency. “Delta-sigma modulators” are also commonly referred to using other interchangeable terms such as “sigma-delta modulators”, “delta-sigma converters”, “sigma delta converters”, “data converters”, “noise shapers”, as well as full and partial combinations of the foregoing terms.
FIG. 1 depicts a conventional topology of an analog-to-digital converter (ADC) 100 that converts input signal, Vin, into a digital output signal, D. The quantizer 108 of ADC delta sigma modulator 101 quantizes the output signal L(z) of loop filter 106 to generate an M-bit quantizer output signal Y corresponding to input signal Vin. “M” is an integer greater than zero and represents the number of bits used by quantizer 108 to quantize the output signal L(z) of loop filter 106 The ADC delta sigma modulator 100 represents output signal Y as a series of low resolution pulses whose average value over time represents delta sigma modulator input signal Vin. In a one-bit delta sigma modulator, the quantizer 108 quantizes the output signal of filter 106 as either a logical +1 or −1, and multi-bit quantizers use multiple bits to quantize the output signal of filter 106. The delta sigma modulator 100 includes an adder 102 to add the input signal Vin to a negative of an analog feedback signal, Vfb. Delta sigma modulator 100 includes a delay element represented by z−1 in a feedback loop to feed back output signal Y·z−1 (Y(n−1) in the time domain) to DAC 104. The analog feedback signal Vfb represents the output of a digital-to-analog converter (DAC) 104. The summer 102 adds Vin and (−Vfb) to determine a difference signal, Vdiff, i.e. Vdiff=Vin−Vfb. In at least one embodiment, summer 102 is a node of loop filter 106 connected to a parallel resistor array that received the input signal Vin and feedback signal fb. Loop filter 106 with a transfer function H(z) filters difference signal, Vdiff, to shift quantization noise signals out of the baseband, e.g. 0 Hz to 20 kHz for audio applications. In one embodiment, filter 106 includes N, series connected integrators and a feedforward summer, where N is an integer greater than or equal to 1. A digital filter 110 processes the output signal Y to provide a multi-bit output at a lower rate than the operational rate of ADC delta sigma modulator 100 by filtering out out-of-band noise.
The quantizer 108 produces a quantization error E(z), which represents noise produced by the delta sigma modulator 100. The Nth order delta sigma modulator output signal Y can be defined in terms of the input signal Vin and a quantization error E(z), the STF, and the NTF as set forth in the z-domain Equation [1]:Y(z)=STF(z)·Vin(z)+NTF(z)·E(z)   [1].
Delta sigma modulators can be implemented using a vast array of configurations that are well discussed extensively in the literature such as Delta Sigma Data Converters—Theory, Design, and Simulation, Norsworthy, Schreier, and Temes, IEEE Press (1997) and Understanding Delta-Sigma Data Converters, Schreier and Temes, IEEE Press (2005).
FIG. 2 depicts a digital-to-analog converter (DAC) signal processing system 200 described in commonly assigned U.S. Pat. No. 6,727,832, entitled “Data Converters with Digitally Filtered Pulse Width Modulation Output Stages and Methods and Systems Using the Same”, with the same inventor John L. Melanson. DAC signal processing system 200 converts an input signal 202 generated by signal source 204 into an output signal 208. The signal source 204 can be any data signal source such as a compact disk player, a digital versatile disk player, and other audio signal sources. The input signal 202 generally undergoes pre-processing by preprocessor 206. In an audio system context, in preparation for processing by delta sigma modulator 210, pre-processing generally involves over-sampling input signal 202. Thus, for an audio signal sampled at 48 kHz and an oversampling ratio of 128:1, pre-processor 206 generates an input signal x(n) (“X(z)” in the z-domain) with a sampling frequency of 6.144 MHz.
The delta sigma modulator 200 includes an M-bit quantizer 212 that quantizes an output signal L(z) of loop filter 214 and generates an output signal Y(z). The delta sigma modulator 210 also has a signal transfer function (STF) and a noise transfer function (NTF) to process output signal Y(z)·z−1 and the input signal X(z). “z−1” represents a delay of one clock cycle in the z-domain. The output signal Y(z) generally relates to the input signal X(z) and quantization error E(z) in accordance with Equation [1], which is reproduced below for convenience:Y(z)=STF(z)·Vin(z)+NTF(z)·E(z)   [1].
Post-processor 216 includes pulse width modulator 218 and a low pass finite impulse response (FIR) filter 220 to drive out-of-band noise to a low level. In at least one embodiment, FIR filter 220 is a comb type filter or the convolution of two or more comb filters. At least one embodiment of the combination of a pulse width modulator 218 and FIR filter 220 is described in U.S. Pat. Nos. 6,727,832, 6,150,969, and 5,815,102, inventor John L. Melanson, which are hereby incorporated by reference in their entirety. In at least one embodiment, the transfer function of FIR filter 220 is designed as a low-pass filter to provide zeros at of out-of-band frequencies with non-trivial amplitudes. For example, in at least one embodiment, the transfer function of FIR filter 220 provides zeros at frequencies corresponding to operational frequencies and corresponding harmonic frequencies of the pulse width modulator 218. The combination of pulse width modulator 218 and FIR filter 220 produces an output signal 116 with high accuracy and low out-of-band noise. Thus, the output signal 116 exhibits low sensitivity to jitter and to convolution with system noise.
It would be desirable to include the filtering capabilities of the pulse width modulator 218 and FIR filter 220 combination in the feedback loop of an ADC delta sigma modulator to filter the output signal of DAC 104 of FIG. 1. However, many features of digital-to-analog converter (DAC) delta sigma modulators do not necessarily translate well into analog-to-digital converter delta sigma modulator. For example, the pulse width modulator 218 and FIR filter 220 combination include delays, such as delays caused by the length of the response of pulse width modulator 218 and delays inherent in FIR filter 220. Such delays can cause an ADC delta sigma modulator to become unstable.